AutoBridge

AutoBridge improves the frequency performance of FPGA designs generated by high-level synthesis (HLS) by combining coarse-grained floorplanning with pipelining to identify and mitigate long interconnect delays, including die-crossing links on multi-die FPGAs.

Key Features:

• Coarse-grained floorplanning: Provides global physical-layout guidance to HLS tools to inform placement and distribution decisions.
• HLS-phase pipelining insertion: Inserts pipeline stages during HLS compilation to break long interconnects and improve timing.
• Long-interconnect identification: Detects long routing paths, with emphasis on inter-die crossings, for targeted pipelining.
• Die-aware logic distribution: Distributes logic across multiple FPGA dies to avoid aggressive packing on a single die.
• Routing-congestion mitigation: Reduces local routing congestion and timing degradation by guiding placement and pipelining.
• Latency-preserving analysis: Applies analysis and algorithms to constrain added pipeline latency so overall throughput is maintained.
• Multi-die FPGA support: Targets advanced multi-die FPGA architectures and their interconnect characteristics.
• CAD toolflow integration: Integrates into existing CAD toolflows for Xilinx FPGAs to apply floorplanning and pipelining during HLS compilation.

Scientific Applications:

• Frequency optimization of HLS designs: Demonstrated an average frequency improvement from 147 MHz to 297 MHz (102% increase) across 43 design configurations.
• Rescuing unroutable designs: Enabled 16 previously unroutable designs to become routable with an average frequency of 274 MHz on Xilinx FPGAs.
• Throughput-preserving performance scaling: Achieves significant frequency gains without loss of throughput and with negligible changes in resource utilization.

Methodology:

Combine coarse-grained floorplanning with pipelining during HLS compilation; provide HLS tools with global physical-layout insights; identify and pipeline long interconnects (particularly die-crossing links); and apply analysis and algorithms to bound added latency while integrating into Xilinx CAD toolflows.