n-BQ-NN

n-BQ-NN implements an n-bit quantization learning framework that constrains neural network weights to powers of two to enable shift-based computation for efficient FPGA inference while preserving full-precision accuracy.

Key Features:

• n-Bit Quantization: Constrains weights to powers of two to enable representation with n-bit quantization and use of shift operations instead of multiplications.
• Gradient Reconstruction: Employs a reconstructed gradient function in back-propagation to compute real gradients and mitigate gradient vanishing in quantized neural networks.
• Shift-Based Computation: Replaces multiplications with bit-shift operations during inference to reduce DSP usage on FPGAs.
• Shift Vector Processing Element (SVPE): Uses an SVPE array that substitutes 16-bit multiplicative operations with shifts in convolutional layers, reducing energy consumption by approximately 31.3% compared to conventional VPEs.
• FPGA Implementation and Performance: Demonstrated on the Xilinx ZCU102 platform with a 2.9× inference speedup over traditional VPE implementations and reduced DSP resource consumption.
• Supported Architectures and Datasets: Evaluated with ResNet, DenseNet, and AlexNet on CIFAR10, CIFAR100, and ImageNet achieving accuracies comparable to full-precision models.

Scientific Applications:

• Image Classification Benchmarks: Quantizes networks for CIFAR10, CIFAR100, and ImageNet to assess classification accuracy against full-precision baselines.
• FPGA-Based Inference Acceleration: Enables deployment of ResNet, DenseNet, and AlexNet on FPGAs for resource-constrained, energy-efficient inference.

Methodology:

Weights constrained to powers of two (n-bit quantization), reconstructed gradient function within back-propagation for real gradient computation, shift operations replacing multiplications during inference, and SVPE arrays replacing 16-bit multipliers in convolutional layers.